Amplifier Offset And Compensation Patent Application (2024)

U.S. patent application number 15/948398 was filed with the patent office on 2019-10-10 for amplifier offset and compensation.The applicant listed for this patent is Infineon Technologies Austria AG. Invention is credited to Keng Chen, Luca Petruzzi.

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AMPLIFIER OFFSET AND COMPENSATION

Abstract

An apparatus includes a first amplifier, a second amplifier, anda compensation-setting generator to generate a first amplifiercompensation setting and second amplifier compensation setting. Acontroller is operable to: i) apply the first amplifiercompensation setting to the first amplifier and apply the secondamplifier compensation setting to the second amplifier. Thecontroller is further operable to switch between generating updatesto the first amplifier compensation setting and the secondamplifier compensation setting.

Claims

1. An apparatus comprising: a first amplifier; a second amplifier;and a controller operable to: i) apply a first differentialcompensation setting to the first amplifier and apply a seconddifferential compensation setting to the second amplifier, and ii)switch between generating updates to the first differentialcompensation setting applied to the first amplifier and the seconddifferential compensation setting applied to the secondamplifier.

2. The apparatus as in claim 1 further comprising: acompensation-setting generator operable to generate the firstdifferential compensation setting and the second differentialcompensation setting; and wherein the controller is furtheroperable to, in different time slots, switch between controllingthe compensation-setting generator to generate the updates to thefirst differential compensation setting and the second differentialcompensation setting.

3. The apparatus as in claim 1 further comprising: acompensation-setting generator operable to generate the firstdifferential compensation setting and the second differentialcompensation setting; and wherein both the first amplifier and thesecond amplifier operate in a continuous amplification mode ofamplifying a respective received signal while thecompensation-setting generator generates the first differentialcompensation setting and the second differential compensationsetting.

4. The apparatus as in claim 1, wherein the first differentialcompensation setting corrects an input offset voltage associatedwith the first amplifier; and wherein the second differentialcompensation setting corrects an input offset voltage associatedwith the second amplifier.

5. The apparatus as in claim 1 further comprising: a firstcompensator operable to provide first compensation to the firstamplifier based on the first differential compensation setting; asecond compensator operable to provide second compensation to thesecond amplifier based on the second compensation setting; whereinthe first amplifier is a first multistage amplifier including arespective first amplifier stage coupled to drive a respectivesecond amplifier stage, the first compensator operable to apply thefirst differential compensation setting to at least one nodecoupling the respective first amplifier stage to the respectivesecond amplifier stage of the first amplifier; and wherein thesecond amplifier is a second multistage amplifier including acorresponding first amplifier stage coupled to drive acorresponding second amplifier stage of the second amplifier, thesecond compensator operable to apply the second differentialcompensation setting to at least one node coupling thecorresponding first amplifier stage to the corresponding secondamplifier stage of the second amplifier.

6. The apparatus as in claim 5, wherein the first compensator is atransconductance amplifier operable to produce a first differentialcorrection signal applied to first differential nodes coupling therespective first stage of the first amplifier to the respectivesecond stage of the first amplifier; and wherein the secondcompensator is a transconductance amplifier operable to produce asecond differential correction signal applied to seconddifferential nodes coupling the corresponding first stage of thesecond amplifier to the corresponding second stage of the secondamplifier.

7. The apparatus as in claim 1 further comprising: acompensation-setting generator operable to generate the firstdifferential compensation setting and the second differentialcompensation setting, the compensation-setting generator operableto repeatedly generate and update the first differentialcompensation setting and the second differential compensationsetting in accordance with a cyclical time slot schedule.

8. The apparatus as in claim 7, wherein the cyclical time slotschedule is implemented based at least in part on a control signaloperable to control generation of an output voltage from a powerconverter.

9. The apparatus as in claim 1 further comprising: acompensation-setting generator operable to generate the firstdifferential compensation setting and the second differentialcompensation setting, the controller further operable to: i)selectively couple an input of the first amplifier to thecompensation-setting generator to produce the first differentialcompensation setting, and ii) selectively couple an input of thesecond amplifier to the compensation-setting generator to producethe second differential compensation setting.

10. The apparatus as in claim 1 further comprising: acompensation-setting generator controlled by the controller, thecompensation setting generator operable to generate the firstdifferential compensation setting and the second differentialcompensation setting; wherein the controller, when generating thefirst differential compensation setting, is operable to:electrically decouple the compensation-setting generator from thesecond amplifier, and ii) electrically couple thecompensation-setting generator to an input of the first amplifier;and wherein the controller, when generating the second differentialcompensation setting, is operable to: electrically decouple thecompensation-setting generator from the first amplifier, and ii)electrically couple the compensation-setting generator to an inputof the second amplifier.

11. The apparatus as in claim 1 further comprising: a firstcompensator operable to provide first compensation to the firstamplifier based on the first differential compensation setting; asecond compensator operable to provide second compensation to thesecond amplifier based on the second differential compensationsetting; wherein the first compensator includes: i) a first storagecircuit operable to store the first differential compensationsetting, and ii) a first transconductance compensation amplifieroperable to drive the first amplifier with a first differentialcorrection signal whose magnitude depends on a magnitude of thefirst differential compensation setting stored in the first storagecircuit; and wherein the second compensator includes: i) a secondstorage circuit operable to store the second differentialcompensation setting, and ii) a second transconductancecompensation amplifier operable to drive the second amplifier witha second differential correction signal whose magnitude depends ona magnitude of the second differential compensation setting storedin the second storage circuit.

12. The apparatus as in claim 11 further comprising: acompensation-setting generator controlled by the controller togenerate the first differential compensation setting and the seconddifferential compensation setting, the compensation-settinggenerator including an offset compensator, a transconductanceamplifier stage, and a third storage circuit; wherein the thirdstorage circuit is operable to store a third differentialcompensation setting derived by the transconductance amplifierstage of the compensation-setting generator, the transconductanceamplifier stage of the compensation-setting generator operable tooutput a correction signal whose magnitude depends on a magnitudeof the third differential compensation setting stored in the thirdstorage circuit.

13. The apparatus as in claim 1 further comprising: a firstcompensator operable to generate a first correction signal based onthe first differential compensation setting, the first compensatorproviding input offset voltage correction to the first amplifiervia application of the first differential correction signal to arespective output of the first amplifier; and a second compensatoroperable to generate a second correction signal based on the seconddifferential compensation setting, the second compensator providinginput offset voltage correction to the second amplifier viaapplication of the second correction signal to a correspondingoutput of the second amplifier.

14. A method comprising: applying a first differential compensationsetting to a first amplifier; applying a second differentialcompensation setting to a second amplifier; and switching betweenupdating the first differential compensation setting applied to thefirst compensator and the second differential compensation settingapplied to the second amplifier.

15. (canceled)

16. The method as in claim 14 further comprising: operating thefirst amplifier and the second amplifier in a continuousamplification mode of amplifying respective received signals whilerepeatedly switching between updating the first differentialcompensation setting and the second differential compensationsetting.

17. (canceled)

18. (canceled)

19. The method as in claim 14 further comprising: repeatedlygenerating and updating the first differential compensation settingapplied to the first amplifier and the second differentialcompensation setting applied to the second amplifier in accordancewith a cyclical schedule; and implementing the cyclical schedulebased at least in part on a control signal controlling generationof an output voltage from a power converter.

20. (canceled)

21. (canceled)

22. (canceled)

23. The method as in claim 14 further comprising: storing the firstdifferential compensation setting in a first storage circuit;inputting the first differential compensation setting in the firststorage circuit into a first compensator, the first compensatordriving the first amplifier with a first correction signal whosemagnitude depends on a magnitude of the first differentialcompensation setting stored in the first storage circuit; storingthe second differential compensation setting in a second storagecircuit; and inputting the second differential compensation settingin the second storage circuit into a second compensator, the secondcompensator driving the second amplifier with a second correctionsignal whose magnitude depends on a magnitude of the secondamplifier compensation setting stored in the second storagecircuit;

24. The method as in claim 14 further comprising: generating afirst correction signal based on the first differentialcompensation setting, the first correction signal providing inputoffset voltage correction to the first amplifier; and generating asecond correction signal based on the second differentialcompensation setting, the second correction signal providing inputoffset voltage correction to the second amplifier.

25. Computer-readable storage hardware having instructions storedthereon, the instructions, when carried out by computer processorhardware, cause the computer processor hardware to: apply a firstdifferential compensation setting to a first amplifier; apply asecond differential compensation setting to a second amplifier; andswitch between updating the first differential compensation settingapplied to the first amplifier and updating the second differentialcompensation setting applied to the second amplifier.

26. The apparatus as in claim 1 further comprising: a firstcompensator operable to generate a first differential correctionsignal from the first differential compensation setting, the firstcompensator operable to apply the first differential correctionsignal to a differential output of the first amplifier; and asecond compensator operable to generate a second differentialcorrection signal from the second differential compensationsetting, the second compensator operable to apply the seconddifferential correction signal to a differential output of thesecond amplifier.

27. The apparatus as in claim 26, wherein the first differentialcorrection signal is a first differential current signal, the firstdifferential current signal including a respective invertingcurrent output and a respective non-inverting current outputapplied to the differential output of the first amplifier, thefirst differential correction signal operable to reduce effects ofan input offset voltage associated with the first amplifier; andwherein the second differential correction signal is a seconddifferential current signal, the second different current signalincluding a corresponding inverting current output and acorresponding non-inverting current output applied to thedifferential output of the second amplifier, the seconddifferential correction signal operable to reduce effects of aninput offset voltage associated with the second amplifier.

28. The apparatus as in claim 27, wherein the respective invertingcurrent output of the first differential current signal flows in anopposite direction than the respective non-inverting current outputof the first differential signal; and wherein the correspondinginverting current output of the second differential current signalflows in an opposite direction than the corresponding non-invertingcurrent output of the second differential signal.

29. The apparatus as in claim 1, wherein the first amplifier is afirst transconductance amplifier; wherein the second amplifier is asecond transconductance amplifier; wherein the first differentialcompensation setting controls a magnitude of a first differentialcurrent signal applied to an output of the first transconductanceamplifier; and wherein the second differential compensation settingcontrols a magnitude of a second differential current signalapplied to an output of the second transconductance amplifier.

30. The apparatus as in claim 1 further comprising: acompensation-setting generator controlled by the controller, thecompensation-setting generator including an auxiliarytransconductance amplifier operable to generate the firstdifferential compensation setting and the second differentialcompensation setting, the compensation-setting generator includinga storage circuit; and wherein the compensation-setting generatorstores a differential voltage in the storage circuit, thedifferential voltage in the storage circuit providing offsetcorrection to the auxiliary transconductance amplifier in thecompensation-setting generator when the compensation-settinggenerator produces the first differential compensation setting andthe second differential compensation setting.

31. The apparatus as in claim 30, wherein the compensation-settinggenerator produces the differential voltage stored in the storagecircuit in between operations of generating an update to the firstdifferential compensation setting and generating an update to thesecond differential compensation setting.

32. The apparatus as in claim 1, wherein the controller is operableto update the first differential compensation setting based on aninput to the first amplifier while the first amplifier produces afirst output signal based on the input to the first amplifier; andwherein the controller is operable to update the seconddifferential compensation setting based on an input to the secondamplifier while the second amplifier produces a second outputsignal based on the input to the second amplifier.

33. The apparatus as in claim 32, wherein the controller isoperable to produce a third differential compensation setting inbetween operations of updating the first differential compensationsetting and updating the second differential compensation setting,the third differential compensation setting correcting an offset ofa transconductance amplifier in a compensation-setting generatorproducing the first differential compensation setting and thesecond differential compensation setting.

Description

BACKGROUND

[0001] Conventional circuits may include one or more amplifiers toamplify a respective input signal. In general, an amplifier is anelectronic device to increase the power or magnitude of a signal (atime-varying voltage or current). An amplifier typically useselectric power from a power supply to amplify the amplitude of areceived signal to produce a respective amplified output signal. Anamplified output signal can be used for any of multiple purposessuch as drive an audio speaker, display screen, etc.

[0002] One type of amplifier is an operational amplifier. Anoperational amplifier (or sometimes referred to as an op-amp) is anIntegrated Circuit (IC) that operates as a voltage amplifier. Anop-amp has a differential input. That is, it has two inputs ofopposite polarity. In certain instances, an op-amp has a singleoutput and a very high gain, which means that the output signal ismuch higher than input signal. External passive components such asresistors, capacitors, etc., can be coupled to the operationalamplifier to control its behavior and provide a desired output.

[0003] One attribute of an operational amplifier is its inputreferred offset voltage, which potentially cause amplificationerrors if it is a high value. Ideally, the input referred offsetvoltage associated with an operational amplifier is zero.

[0004] In conventional power management IC design, three commonmethods are used to correct input referred offset of a respectiveoperational amplifier. For example, conventional methodsinclude:

[0005] 1.) Using large resistor chain as well as iDAC to minimizeinput referred offset. The disadvantage of this method is largespace consumption; moreover, the trim process will also add cost tomanufacture.

[0006] 2.) Using an auxiliary amplifier to sensing/correcting theinput referred offset voltage of targeting amplifier. Thedisadvantage of this method is each targeting amplifier needs anauxiliary amplifier which leads to large space consumption anddesign complexity; moreover, as the auxiliary amplifier need to beoperated between auto zero phase and amplification phase, itrequires a dedicated clock circuit.

[0007] 3.) Using a chopping method in which the polarity of aninput signal to the target amplifier needs to be constantlychanged. The disadvantage of this method is the required change inpolarity; it also requires a filter to be designed to filter outthe switching noise.

BRIEF DESCRIPTION

[0008] Embodiments herein include novel ways of improving anaccuracy of providing amplification and reducing affects of theinput referred offset voltage.

[0009] More specifically, embodiments herein include a novelapparatus (such as hardware, circuitry, device, etc.) including afirst amplifier, a second amplifier, and a compensation-settinggenerator to generate a first amplifier compensation setting andsecond amplifier compensation setting.

[0010] The novel apparatus further includes a controller operableto: i) apply (input) the first generated amplifier compensationsetting to the first amplifier to provide compensation and apply(input) the second generated amplifier compensation setting to thesecond amplifier to provide compensation.

[0011] In accordance with further embodiments, the system asdiscussed herein includes a first compensator (associated with thefirst amplifier) and a second compensator (associated with thesecond amplifier). To provide compensation such as correction of aninput referred offset voltage associated with the first amplifier(such as a multi-stage amplifier including a transconductance inputamplifier stage), the first compensator generates a firstcorrection output based on the first compensation setting andapplies the first correction output to the first amplifier. Toprovide compensation such as correction of an input referred offsetvoltage associated with the second amplifier (such as a multi-stageamplifier including a transconductance input amplifier stage), thesecond compensator generates a second correction output based onthe second compensation setting and applies it to the secondamplifier.

[0012] To ensure more accurate amplification over time, thecontroller can be configured to switch between generating updatesto the first amplifier compensation setting applied to the firstcompensator and the second amplifier compensation setting appliedto the second amplifier.

[0013] More specifically, in accordance with further embodiments,the controller is operable to, in different time slots, switchbetween controlling the compensation-setting generator to generatethe updates to the first amplifier compensation setting and thesecond amplifier compensation setting.

[0014] As previously discussed, the first amplifier compensationsetting corrects an input (referred) offset voltage associated withthe first amplifier. The second amplifier compensation settingcorrects an input (referred) offset voltage associated with thesecond amplifier. Continually updating the first amplifiercompensation setting (value) and the second amplifier compensationsetting (value) (such as in different time slots) ensures moreaccurate compensation of input referred offset associated with thefirst amplifier and the second amplifier.

[0015] Note further that the compensation-setting generator can beconfigured to generate the first amplifier compensation setting andthe second amplifier compensation setting in any suitable manner,and according to any suitable schedule. In one embodiment, thecontroller is operable to control the compensation-settinggenerator to repeatedly generate and update the first amplifiercompensation setting and the second amplifier compensation settingin accordance with a cyclical time slotted schedule, switchingbetween generating an update to the first amplifier compensationsetting and an update to the second amplifier compensationsetting.

[0016] A single compensation-setting generator can be configured toproduce any number of compensation settings for any number ofamplifiers. In accordance with a time slotted schedule, thecompensation setting generator can be configured to generaterespective compensation settings in a cyclical manner such thateach of the compensation settings is constantly updated overtime.

[0017] The cyclical schedule of repeatedly generating updated tocompensation settings can be implemented based on any suitableclock signal. In one embodiment, the controller controls generationof the cyclical time slotted schedule based at least in part on acontrol output such as a PWM (Pulse With Modulation) control signalof a power supply that is used to control generation of an outputvoltage from a respective power converter circuit of the powersupply.

[0018] In accordance with further embodiments, both the firstamplifier and the second amplifier operate in a continuousamplification mode of amplifying a respective received signal toproduce corresponding output (signals) while thecompensation-setting generator switches between generating thefirst amplifier compensation setting and the second amplifiercompensation setting.

[0019] In yet further embodiments, the first amplifier is a firstmultistage amplifier including a respective first amplifier stagecoupled to drive a respective second amplifier stage. The firstcompensator is operable to drive at least one node coupling therespective first amplifier stage to the respective second amplifierstage of the first amplifier. The second amplifier is optionally asecond multistage amplifier including a corresponding firstamplifier stage coupled to drive a corresponding second amplifierstage of the second amplifier. The second compensator is operableto drive at least one node coupling the corresponding firstamplifier stage to the corresponding second amplifier stage of thesecond amplifier.

[0020] Each of the first compensator and the second compensator canbe of any suitable type. In one non-limiting example embodiment,the first compensator is a transconductance amplifier operable tooutput current to at least one node coupling the respective firststage of the first amplifier to the respective second stage of thefirst amplifier. The second compensator is optionally atransconductance amplifier operable to output current to the atleast one node coupling the corresponding first stage of the secondamplifier to the second stage of the second amplifier.

[0021] In one non-limiting example embodiment, to generate thefirst amplifier compensation setting and the second amplifiercompensation setting, the controller is operable to: i) selectivelycouple an input of the first amplifier to the compensation-settinggenerator to produce the first compensation setting, and ii)selectively couple an input of the second amplifier to thecompensation-setting generator to produce the second compensationsetting. In a manner as previously discussed, the generation of theamplifier compensation settings can be done in different timeslots.

[0022] In accordance with further embodiments, when generating thefirst compensation setting, the controller is operable to:electrically decouple the compensation-setting generator from thesecond amplifier, and ii) electrically couple thecompensation-setting generator to an input of the firstamplifier.

[0023] When generating the second compensation setting, thecontroller is operable to: electrically decouple thecompensation-setting generator from the first amplifier, and ii)electrically couple the compensation-setting generator to an inputof the second amplifier.

[0024] The first compensator and the second compensator can beconfigured in any suitable manner to provide compensation. In oneexample embodiment, the first compensator includes: i) a firststorage circuit to store the first amplifier compensation setting,and ii) a first transconductance compensation amplifier to drivethe first amplifier with a correction output whose magnitudedepends on a magnitude of the first amplifier compensation settingstored in the first storage circuit. The second compensatorincludes: i) a second storage circuit to store the second amplifiercompensation setting, and ii) a second transconductancecompensation amplifier to drive the second amplifier with acorrection output whose magnitude depends on a magnitude of thesecond amplifier compensation setting stored in the second storagecircuit.

[0025] Embodiments herein are useful over conventional techniques.For example, certain embodiments herein require only one offsetcorrection circuit (compensation setting generator) to compensatethe input referred offset voltage associated with each of multipleamplifiers. Thus, one embodiment herein includes sharing one offsetcompensator between multiple targeting amplifiers, which will savevaluable circuit board area as well as cost of components. Whenimplemented in power management POL circuit, direct use of PWMsignal (as an input to the controller) will also eliminatedesigning oscillator circuit, which further improves the simplicityof the design.

[0026] These and other more specific embodiments are disclosed inmore detail below.

[0027] Note that techniques as discussed herein can be implementedin any suitable environment such as amplifier circuitry, powersupplies, multi-phase power supply applications, single phase pointof load (a.k.a., POL) power supply applications, etc.

[0028] Note further that although embodiments as discussed hereinare applicable to multi-phase power supply circuits such as thoseimplementing buck converters, DC-DC converter phases, the conceptsdisclosed herein may be advantageously applied to any othersuitable topologies as well as general power supply controlapplications.

[0029] Additionally, note that embodiments herein can includecomputer processor hardware (that executes corresponding switchinstructions) to carry out and/or support any or all of the methodoperations disclosed herein. In other words, one or morecomputerized devices or processors (computer processor hardware)can be programmed and/or configured to operate as explained hereinto carry out different embodiments of the invention.

[0030] Yet other embodiments herein include software programs toperform the steps and operations summarized above and disclosed indetail below. One such embodiment comprises a computer programproduct that has non-transitory computer-storage media (e.g.,memory, disk, flash, . . . ) including computer programinstructions and/or logic encoded thereon that, when performed in acomputerized device having a processor and corresponding memory,programs the processor to perform any of the operations disclosedherein. Such arrangements are typically provided as softwareinstructions, code, and/or other data (e.g., data structures)arranged or encoded on a computer readable storage medium ornon-transitory computer readable media such as an optical medium(e.g., CD-ROM), floppy or hard disk or other a medium such asfirmware or microcode in one or more ROM or RAM or PROM chips, anApplication Specific Integrated Circuit (ASIC), circuit logic, etc.The software or firmware or other such configurations can beinstalled onto a respective controller circuit to cause thecontroller circuit (such as logic) to perform the techniquesexplained herein.

[0031] Accordingly, one embodiment of the present disclosure isdirected to a computer program product that includes a computerreadable medium having instructions stored thereon for supportingoperations such as controlling one or more phases in a powersupply. For example, in one embodiment, the instructions, whencarried out by computer processor hardware (one or more computerdevices, control logic, digital circuitry, etc.), cause thecomputer processor hardware to: generate a first amplifiercompensation setting and a second amplifier compensation setting(during different time slots), the first amplifier compensationsetting generated to correct an input offset voltage associatedwith a first amplifier, the second amplifier compensation settinggenerated to correct an input offset voltage associated with asecond amplifier; apply/input the first compensation setting to afirst compensator, the first compensator providing compensation tothe first amplifier; apply/input the second compensation setting toa second compensator, the second compensator providing compensationto the second amplifier; and switch between updating the firstcompensation setting applied to the first compensator and thesecond compensation setting applied to the second amplifier.

[0032] The ordering of the operations has been added for claritysake. The operations can be performed in any suitable order.

[0033] It is to be understood that the system, method, device,apparatus, logic, etc., as discussed herein can be embodiedstrictly as hardware (such as analog circuitry, digital circuitry,logic, etc.), as a hybrid of software and hardware, or as softwarealone such as within a processor, or within an operating system ora within a software application.

[0034] Note that although each of the different features,techniques, configurations, etc., herein may be discussed indifferent places of this disclosure, it is intended, whereappropriate, that each of the concepts can optionally be executedindependently of each other or in combination with each other.Accordingly, the one or more present inventions as described hereincan be embodied and viewed in many different ways.

[0035] Also, note that this preliminary discussion of embodimentsherein purposefully does not specify every embodiment and/orincrementally novel aspect of the present disclosure or claimedinvention(s). Instead, this brief description only presents generalembodiments and corresponding points of novelty over conventionaltechniques. For additional details and/or possible perspectives(permutations) of the invention(s), the reader is directed to theDetailed Description section and corresponding figures of thepresent disclosure as further discussed below.

BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The foregoing and other objects, features, and advantages ofthe invention will be apparent from the following more particulardescription of preferred embodiments herein, as illustrated in theaccompanying drawings in which like reference characters refer tothe same parts throughout the different views. The drawings are notnecessarily to scale, with emphasis instead being placed uponillustrating the embodiments, principles, concepts, etc.

[0037] FIG. 1 is an example diagram illustrating compensatedamplifiers according to embodiments herein.

[0038] FIG. 2 is an example diagram of an apparatus providingamplifier compensation according to embodiments herein.

[0039] FIG. 3 is an example timing-diagram of controlling arespective compensation-setting generator according to embodimentsherein.

[0040] FIG. 4 is an example diagram illustrating automatic zeroing(calibration) of a compensation-setting generator according toembodiments herein.

[0041] FIG. 5 is an example diagram illustrating generation of afirst amplifier compensation setting according to embodimentsherein.

[0042] FIG. 6 is an example diagram illustrating an automaticzeroing (calibration) of the compensation-setting generatoraccording to embodiments herein.

[0043] FIG. 7 is an example diagram illustrating generation of asecond amplifier compensation setting according to embodimentsherein.

[0044] FIG. 8 is an example diagram illustrating an amplifier andcompensator according to embodiments herein.

[0045] FIG. 9 is an example diagram illustrating acompensation-setting generator according to embodiments herein.

[0046] FIG. 10 is an example diagram illustrating computerprocessor hardware and related software instructions or logiccircuit to execute methods according to embodiments herein.

[0047] FIG. 11 is an example diagram illustrating a methodaccording to embodiments herein.

[0048] FIG. 12 is an example diagram illustrating a compensatedamplifier according to embodiments herein.

[0049] FIG. 13 is an example diagram illustrating a compensatedamplifier according to embodiments herein.

DETAILED DESCRIPTION

[0050] Now, more specifically, FIG. 1 is an example diagram of anapparatus 100 according to embodiments herein.

[0051] As shown, the apparatus 100 (which can be embodied in anysuitable form such as hardware, circuitry, device, etc.) includescontroller 140, compensation-setting generator 110, compensator121, compensator 122, amplifier 131, and amplifier 132. Thus, eachof these resources can be implemented as hardware, circuitry, adevice, etc.

[0052] In general, the controller 140 generates control output 145(one or more control signals) to control compensation-settinggenerator 110 and generation of amplifier compensation setting 111and amplifier compensation setting 112. The first amplifiercompensation setting 111 is generated to correct (or reduce)affects of an input (referred) offset voltage associated with thefirst amplifier 131. The second amplifier compensation setting isgenerated to correct or reduce affects of an input (referred)offset voltage associated with the second amplifier 132

[0053] Thus, the first amplifier compensation setting 111 providescorrection to an input offset voltage associated with the firstamplifier 131; the second amplifier compensation setting 112corrects an input offset voltage associated with the secondamplifier.

[0054] During operation, as its name suggests, the firstcompensator 121 provides compensation to first amplifier 131 basedon amplifier compensation setting 111. The second compensatorprovides compensation to second amplifier 132 based on amplifiercompensation setting 112.

[0055] The compensation-setting generator 110 generates a firstamplifier compensation setting 111 and second amplifiercompensation setting 112. The controller is operable to: i) apply(input) the first amplifier compensation setting 111 to the firstcompensator 121 and apply (input) the second amplifier compensationsetting 112 to the second compensator 122.

[0056] To ensure more accurate amplification over time, thecontroller 140 is operable to repeatedly switch between generatingupdates to the first amplifier compensation setting 111 inputted tothe first compensator 121 and the second amplifier compensationsetting 112 inputted to the second compensator 122.

[0057] In one embodiment, the compensator 121 can include a storagecircuit or buffer to store the generated first amplifiercompensation setting 111; the compensator 122 can include a storagecircuit or buffer to store the generated first amplifiercompensation setting 111.

[0058] To provide compensation such as correction of an inputreferred offset voltage associated with the first amplifier 131,the first compensator 121 generates a first correction output 261based on the first compensation setting 111 and applies (inputs)the first correction output 261 to the first amplifier 131.

[0059] In a similar manner, to provide compensation such ascorrection of an input referred offset voltage associated with thesecond amplifier 132, the second compensator 122 generates a secondcorrection output 262 based on the second compensation setting 112and applies (inputs) the correction output 262 to the secondamplifier 132.

[0060] In one embodiment, as shown in FIG. 12, the compensator 121is integrated or fabricated as part of the amplifier 131; thecompensator 122 is integrated or fabricated as part of theamplifier 132. In such an instance, via input from the controller140, the compensation setting generator 110 is operable to applythe first amplifier compensation setting 111 to the first amplifier131 to provide respective compensation; the controller 140 isoperable to apply the second amplifier compensation setting 112 tothe second amplifier 132 to provide respective compensation.

[0061] In accordance with further embodiments, as shown in FIG. 13,the compensator 121 is integrated or fabricated as part of thecompensation setting generator 110; additionally, the compensator122 is integrated or fabricated as part of the compensation settinggenerator 110. In such an instance, via input from the controller140, the compensation setting generator 110 is operable to applythe correction output signal 261 to the amplifier 131 to providerespective compensation; the compensation setting generator 110 isoperable to apply the correction output signal 262 to the amplifier132 to provide respective compensation.

[0062] Referring again to FIG. 1, in accordance with furtherembodiments, the controller 140 is operable to generate theamplifier compensation settings 111 and 112 in different timeslots. In such an instance, the controller 140 switches betweencontrolling the compensation-setting generator 110 to generate anupdate to the first amplifier compensation setting 111 and thesecond amplifier compensation setting 112.

[0063] As further described herein, continually updating the firstamplifier compensation setting 111 (value) and the second amplifiercompensation setting 112 (value) ensures more accurate compensationof input referred offset associated with the first amplifier 131and the second amplifier 132. In other words, if the input referredoffset voltage associated with the first amplifier 131 and/or thesecond amplifier 132 changes over time, continuous updating of therespective amplifier compensation setting 111 and amplifiercompensation setting 112 ensures constant correction and thereforemore accurate amplification (via amplifier 131) of the input signal181 into the output signal 191 and more accurate amplification (viaamplifier 132) of the input signal 182 into the output signal192.

[0064] FIG. 2 is an example diagram of an apparatus providingamplifier compensation according to embodiments herein.

[0065] As previously discussed, the compensation-setting generator110 generates the first amplifier compensation setting 111 and thesecond amplifier compensation setting 112. In one embodiment, thecompensation-setting generator 110 controlled by the controller 140includes an offset compensator A4 (such as a linear differentialamplifier), a transconductance amplifier stage A5, and a storagecircuit (capacitors C3 and C4) to generate the amplifiercompensation settings 111 and 112. In alternative embodiments, thestorage circuit is a digital buffer storing a digitalrepresentation of the amplifier compensation setting associatedwith the offset compensator A4.

[0066] As further discussed below, the capacitors C3 and C4 of thecompensation setting generator 110 store an amplifier compensationsetting derived by the transconductance amplifier stage A4 of thecompensation-setting generator 110 during a so-called auto-zeroingphase during which the amplifier A4 of compensation settinggenerator 110 is calibrated. In such an instance, when generating arespective amplifier compensation setting 111 or 112, thetransconductance amplifier stage A4 of the compensation-settinggenerator 110 is operable to produce and output a correction output221 (such as differential output signals 221-1 and 221-2) whosemagnitude depends on a magnitude of the amplifier compensationsetting (voltage) stored in the capacitors C3 and C4 (storagecircuit). Details of calibrating the compensation setting generator110 are further discussed below in FIGS. 3, 4, and 6.

[0067] As further shown in FIG. 2, by way of non-limiting exampleembodiment, the first amplifier 131 is a first multistage amplifierincluding a respective first transconductance amplifier stage 222(Al) coupled to drive a respective second amplifier stage 223(A2).

[0068] In one embodiment, the first transconductance amplifierstage 222 of amplifier 131 is a differential transconductance inputamplifier stage. In accordance with further embodiments, the gainof first transconductance amplifier stage 222 in amplifier 131 issubstantially greater (such as more than 5 times or any othersuitable multiple greater) than a gain of transconductanceamplifier A3. The gain of first transconductance amplifier stage232 (A6) in amplifier 132 is substantially greater (such as morethan 5 times or any other suitable multiple greater) than a gain oftransconductance amplifier A8.

[0069] In general, each of the transconductance amplifiers (such asamplifiers A1, A3, A5, A6, and A8) as discussed herein receives adifferential input voltage. Based on a respective transconductancegain associated with the respective amplifier, and a differentialvoltage inputted across the inverting and non-inverting inputs, thetransconductance amplifiers outputs a differential output current.A magnitude of the output current of the respectivetransconductance amplifier on each differential output is ideallyequal. However, the polarity of the output current is opposite. Forexample, the non-inverting current output from transconductanceamplifier A3 is opposite to inverting current output fromtransconductance amplifier A3. Each of the transconductanceamplifiers operates in a similar manner.

[0070] As further described herein, the output 261 (such asdifferential current) from amplifier A3 provides compensation tothe output of transconductance amplifier A1 to correct the inputreferred offset associated with transconductance amplifier A1; theoutput current 262 (such as differential current) from amplifier A8provides compensation to the output of transconductance amplifierA8 to correct the input referred offset associated withtransconductance amplifier A8.

[0071] The first compensator 121 includes a transconductanceamplifier A3 operable to drive respective correction output 261(such as differential output current signals) to multiple nodes(such as node 231-1 and node 231-2) coupling the respective firsttransconductance amplifier stage 222 of the first amplifier 131 tothe respective second amplifier stage 223 of the first amplifier131.

[0072] A magnitude of the correction output 261 (one or moresignals) outputted by the transconductance amplifier A3 ofcompensator 121 depends on the magnitude of the amplifiercompensation setting 111 (voltage) stored in capacitor C1 and C2(storage circuit) as generated by the compensation settinggenerator 110.

[0073] By way of a further non-limiting example embodiment, thesecond amplifier 132 is a second multistage amplifier including arespective first transconductance amplifier stage 232 (A6) coupledto drive a respective second amplifier stage 233 (A7).

[0074] In one embodiment, the first transconductance amplifierstage 232 of amplifier 132 is a differential transconductance inputamplifier stage. In accordance with further embodiments, the gainof first transconductance amplifier stage 232 in amplifier 132 issubstantially greater (such as more than 5 times greater) than again of amplifier A8. The gain of first transconductance amplifierstage 232 in amplifier 132 is substantially greater (such as morethan 5 times greater) than a gain of transconductance amplifierA8.

[0075] The second compensator 122 includes a transconductanceamplifier A8 operable to drive respective correction output 262(one or more output current signals) to multiple nodes (such asnode 241-1 and node 241-2) coupling the respective first amplifierstage 232 of the second amplifier 132 to the respective secondamplifier stage 233 of the second amplifier 132.

[0076] A magnitude of the correction output 262 outputted by thetransconductance amplifier A8 of compensator 122 depends on themagnitude of the amplifier compensation setting 112 (voltage)stored in capacitor C5 and C6 (storage circuit) as generated by thecompensation setting generator 110.

[0077] In accordance with further embodiments, both the firstamplifier 131 and the second amplifier 132 can be configured tooperate in a continuous amplification mode of amplifying arespective received signal to produce corresponding output signalswhile the compensation-setting generator 110 switches betweengenerating the first amplifier compensation setting 111 and thesecond amplifier compensation setting 112.

[0078] As further shown in FIG. 2, the compensation settinggenerator 110 further includes switches S11, S12, S13, S14, S21,S22, S23, S24, S31, S32, S33, and S34. The controller 140 controlsactivation of the groupings of switches during different controlphases. For example, switches S11, S12, S13, and S14 represents afirst group of switches simultaneously controlled by control output322; switches S21, S22, S23, and S24 represents a second group ofswitches simultaneously controlled by control output 323; switchesS31, S32, S33, and S34 represents a third group of switchessimultaneously controlled by control output 321. Assume that thecontroller produces switch control output 321 to activate the firstgroup of switches including switches S31, S32, S33, and S34. Asfurther discussed below in more detail, activation of switches S31and S32 to ON states causes the reference voltage Vref to beinputted to both the inverting out and non-inverting node ofamplifier A4. The magnitude of Vref can be any suitable value. Ifamplifier A4 was an ideal operational amplifier, applying the sameinput voltage value to both the inverting and non-inverting wouldresult in generation of the same output voltage for voltage 210-1and voltage 210-2. However, due to the input referred offsetvoltage associated with amplifier A4, the magnitude of voltage210-1 and voltage 210-2 are different.

[0079] In this example embodiment during activation of switches S31and S32 to ON states, the amplifier A4 produces a respective outputvoltage 210-1 that is conveyed through switch S33 (activated to ONstate as well) to the inverting input of transconductance amplifierA5 and storage circuit (capacitor C3). Capacitor C3 stores thegenerated voltage 210-1. Additionally, amplifier A4 produces arespective output voltage 210-2 that is conveyed through switch S34(activated to ON state) to the non-inverting input oftransconductance amplifier A5 and storage circuit (capacitor C4).Capacitor C4 stores the voltage 210-2.

[0080] Assume that the controller 140 produces switch controloutput 322 to simultaneously activate the group of switchesincluding switches S11, S12, S13, and S14 to ON states.

[0081] In such an instance, activation of switch S11 to an ON statecauses the input signal 182-1 to be inputted to the non-invertingnode of amplifier A4. Activation of switch S12 to an ON state inphase Q2 causes the input signal 182-2 to be inputted to theinverting node of amplifier A4. Thus, via activation of theswitches S11 and S12 to ON states, the controller 140 is operableto: electrically couple the compensation-setting generator 110 tothe input of the second amplifier 132.

[0082] Further, during activation of the first group of switchesS11, S12, S13, and S14 to ON states, the amplifier A4 produces arespective output voltage 210-1 that is conveyed through switch S13(activated to ON state) to the non-inverting input oftransconductance amplifier A5 and storage circuit (capacitor C5).Capacitor C5 stores the voltage 210-1. The amplifier A4 alsoproduces a respective output voltage 210-2 that is conveyed throughswitch S14 (activated to ON state) to the inverting input oftransconductance amplifier A8 and storage circuit (capacitor C6).Capacitor C6 stores the voltage 210-2.

[0083] The prior stored voltage in capacitors C5 and C6 causes thetransconductance amplifier A8 to provide correction to the voltage210-1 and voltage 210-2 generated by the amplifier A4. Accordingly,the prior stored voltage in capacitors C3 and C4 providescorrection to the amplifier A4 when generating the amplifiercompensation setting 112 stored in capacitors C5 and C6.

[0084] Assume that the controller 140 produces switch controloutput 323 to simultaneously activate the group of switchesincluding switches S21, S22, S23, and S24 to ON states.

[0085] Activation of switch S21 to an ON state in phase Q4 causesthe input signal 181-1 to be inputted to the non-inverting node ofamplifier A4. Activation of switch S22 to an ON state causes theinput signal 181-2 to be inputted to the inverting node ofamplifier A4. Thus, via activation of the switches S21 and S22, thecontroller 140 is operable to: electrically couple thecompensation-setting generator 110 to the input of the firstamplifier 131, and electrically decouple (via deactivation ofswitches S 11 and S12) the compensation-setting generator 110 froman input of the second amplifier 132.

[0086] In such an instance, during simultaneous activation ofswitches S21, S22, S23, and S24, the amplifier A4 produces arespective output voltage 210-1 that is conveyed through switch S23(activated to ON state) to the inverting input of transconductanceamplifier A3 and storage circuit (capacitor C2). Capacitor C2stores the voltage 210-1. The amplifier A4 also produces arespective output voltage 210-2 that is conveyed through switch S24(activated to ON state) to the non-inverting input oftransconductance amplifier A3 and capacitor C1. Capacitor C1 storesthe voltage 210-2.

[0087] The prior stored voltage in capacitors C3 and C4 causes thetransconductance amplifier A5 to provide correction to the voltage210-1 and voltage 210-2 generated by the amplifier A4. Accordingly,the prior stored voltage in capacitors C3 and C4 providescorrection to the amplifier A4 when generating the amplifiercompensation setting 111 stored in capacitors C1 and C2.

[0088] Note that, in one embodiment, amplifiers A3 and A8 in FIG. 2along with the corresponding circuitry C1 and C2, and C5 and C6respectively, are so-called "auxiliary stages," in particular ofthe associated amplifier 131, 132. In such an instance, such ascaptured by FIG. 12, the auxiliary stages A3, and A8 as well ascorresponding circuitry C1, C2, C5, and C6 are potentially part ofthe amplifier 131 for A3, and amplifier 132 for A8. Alternatively,they may form part of the compensation setting generator 110.

[0089] Note that, in one embodiment, amplifiers A3, A5 and A8 inFIG. 2, are so-called "auxiliary stages" associated with thecompensation setting generator 110. In such an instance, such ascaptured by FIG. 13, each of the auxiliary stages A3, A5, and A8,as well as corresponding circuitry C1, C2, C3, C4, C5, and C6 arepotentially part of the compensation-setting generator 110.

[0090] FIG. 3 is an example timing-diagram of controlling arespective compensation-setting generator according to embodimentsherein.

[0091] As previously discussed, the compensation-setting generator110 can be configured to generate the first amplifier compensationsetting 111 and the second amplifier compensation setting 112 inany suitable manner, and according to any suitable schedule.

[0092] In one embodiment, the controller 140 is operable togenerate control output 145 (switch control output 320, 321, and322) to control the compensation-setting generator 110 torepeatedly generate and update the first amplifier compensationsetting 111 (stored in one embodiment as a differential voltage incapacitors C1 and C2) and the second amplifier compensation setting(stored in one embodiment as a differential voltage in capacitorsC5 and C6) in accordance with a cyclical time slotted schedule 300that switches between: i) generating and applying an update to thefirst amplifier compensation setting 111 and ii) generating andapplying an update to the second amplifier compensation setting112.

[0093] Switch control output 321 of schedule 300 controlsactivation/deactivation of switches S31, S32, S33, and S34. Logichigh of switch control output 321 indicates times of activatingthese switches to ON states while logic low indicates times ofdeactivating switches to OFF states.

[0094] Switch control output 322 of schedule 300 controlsactivation/deactivation of switches S11, S12, S13, and S14. Logichigh of switch control output 322 indicates times of activatingthese switches to ON states while logic low indicates times ofdeactivating switches to OFF states.

[0095] Switch control output 323 of schedule 300 controlsactivation/deactivation of switches S21, S22, S23, and S24. Logichigh of switch control output 323 indicates times of activatingthese switches to ON states while logic low indicates times ofdeactivating switches to OFF states.

[0096] The cyclical time slot schedule 300 can be implemented basedon any suitable clock signal. In one embodiment, the controller 140controls generation of the cyclical time slotted schedule based atleast in part on a control signal (clock signal 292 of FIG. 2) suchas a PWM (Pulse With Modulation) control signal of a power supply260 that is used to control generation of an output voltage from arespective power converter circuit.

[0097] In this example embodiment, each calibration cycle includesfour phases, namely, phase Q1, phase Q2, phase Q3, and phaseQ4.

[0098] In phase Q1, such as between time T1 and T2 for cycle #1,the controller 140 produces switch control output 321 to be a highstate to activate the switches S31, S32, S33, and S34 to an ONstate. During phase Q1, the controller 140 produces switch controloutput 322 as a low state to deactivate the switches S11, S12, S13,and S14 to an OFF state. During phase Q1, the controller 140produces switch control output 323 to be in a low state todeactivate the switches S21, S22, S23, and S24 to an OFF state.Note that subsequent FIG. 4 illustrates settings of switches andcircuit connectivity for phase Q1.

[0099] Referring again to FIG. 3, in phase Q2, such as between timeT2 and T3 for cycle #1, the controller 140 produces switch controloutput 322 to be a high state to activate the switches S11, S12,S13, and S14 to an ON state. During phase Q2, the controller 140produces switch control output 323 to be a low state to deactivatethe switches S21, S22, S23, and S24 to an OFF state. During phaseQ2, the controller 140 produces switch control output 321 to be alow state to deactivate the switches S31, S32, S33, and S34 to anOFF state. FIG. 5 illustrates settings of switches and circuitconnectivity for phase Q2.

[0100] Referring again to FIG. 3, in phase Q3, such as between timeT3 and T4 for cycle #1, the controller 140 produces switch controloutput 321 to be a high state to activate the switches S31, S32,S33, and S34 to an ON state. During phase Q3, the controller 140produces switch control output 322 to be a low state to deactivatethe switches S11, S12, S13, and S14 to an OFF state. During phaseQ3, the controller 140 produces switch control output 322 to be alow state to deactivate the switches S21, S22, S23, and S24 to anOFF state. FIG. 6 illustrates settings of switches and circuitconnectivity for phase Q3.

[0101] Referring again to FIG. 3, in phase Q4, such as between timeT4 and T5 for cycle #1, the controller 140 produces switch controloutput 323 to be a high state to activate the switches S21, S22,S23, and S24 to an ON state. During phase Q4, the controller 140produces switch control output 322 to be a low state to deactivatethe switches S21, S22, S23, and S24 to an OFF state. During phaseQ4, the controller 140 produces switch control output 321 to be alow state to deactivate the switches S31, S32, S33, and S34 to anOFF state. FIG. 7 illustrates settings of switches and circuitconnectivity for phase Q4.

[0102] Similar to cycle #1, the controller 140 repeats the controlfor each of multiple cycles (cycle #2, cycle #3, etc.) tocontinuously update both the amplifier compensation setting 111(stored in capacitor C1 and C2) and amplifier compensation setting112 (stored in capacitor C5 and C6) for each cycle. Morespecifically, the amplifier compensation setting 111 stored inrespective storage circuit such as capacitors C1 and C2 is updatedin phase Q4 of each cycle; the amplifier compensation setting 112stored in storage circuit such as capacitors C5 and C6 is updatedin phase Q2 of each cycle.

[0103] In one embodiment, the amplifier 131 and amplifier 132provide non-stop amplification of the input signals 181 and 191even though the amplifier compensation settings are updated duringdifferent portions of each cycle. Accordingly, in one embodiment,the correction output 261 applied to amplifier 131 and thecorrection output 262 applied to amplifier 132 are always updatedto provide proper amplification of input signals 181 and 191 toproduce respective output signals 182 and 192.

[0104] For 3 out of 4 phases of a respective cycle, a magnitude ofa stored amplifier compensation setting is constant. During onephase, a respective amplifier compensation setting is potentiallyupdated to a new value. For example, during phases Q1, Q2, and Q3,the current value of amplifier compensation setting 111 stored inthe storage circuit (such as capacitors C1 and C2) is used as abasis to provide correction of corresponding input referred offsetassociated with the first amplifier 131. The magnitude of theamplifier compensation setting 111 is updated in phase Q4. Theamplifier 131 provides continuous amplification of the input 181into the output 191 throughout each of the multiple phases Q1, Q2,Q3, and Q4.

[0105] During phases Q1, Q3, and Q4, the value of amplifiercompensation setting 112 stored in the storage circuit (such ascapacitors C5 and C6) is used as a basis to provide correction ofcorresponding input referred offset associated with the secondamplifier 132. The magnitude of the amplifier compensation setting112 is updated in phase Q2. The amplifier 131 provides continuousamplification of the input 182 into the output 192 throughout eachof the multiple phases Q1, Q2, Q3, and Q4.

[0106] Embodiments herein are useful over conventional techniques.For example, certain embodiments herein require only one offsetcorrection circuit such as compensation setting generator 110 tocompensate the input referred offset voltage associated withamplifiers 131 and 132. Thus, one embodiment herein includessharing one offset compensator amongst multiple targetingamplifiers, which saves valuable circuit board area as well as costof components otherwise needed to provide compensation. Whenimplemented in power management POL circuit, direct use of PWMsignal (such as an input form a power supply eliminates the needdesign an independent oscillator circuit, which further improvesthe simplicity of a respective amplifier circuit.

[0107] FIG. 4 is an example diagram illustrating automatic-zeroing(calibration) of a compensation-setting generator according toembodiments herein.

[0108] As previously discussed, in phase Q1, such as between timeT1 and T2 for cycle #1, the controller 140 produces switch controloutput 321 to be a high state to activate the group of switchesS31, S32, S33, and S34 to an ON state. During phase Q1, thecontroller 140 produces switch control output 322 as a low state todeactivate the group of switches S11, S12, S13, and S14 to an OFFstate. During phase Q1, the controller 140 produces switch controloutput 323 to be in a low state to deactivate the group of switchesS21, S22, S23, and S24 to an OFF state.

[0109] Activation of switches S31 and S32 to ON states causes thereference voltage Vref to be inputted to both the inverting out andnon-inverting node of amplifier A4. The magnitude of Vref can beany suitable value. If amplifier A4 was an ideal operationalamplifier, applying the same input voltage value to both theinverting and non-inverting would result in generation of the sameoutput voltage for voltage 210-1 and voltage 210-2. However, due tothe input referred offset voltage associated with amplifier A4, themagnitude of voltage 210-1 and voltage 210-2 are different.

[0110] In this example embodiment, during phase Q1, the amplifierA4 produces a respective output voltage 210-1 that is conveyedthrough switch S33 (activated to ON state as well) to the invertinginput of transconductance amplifier A5 and storage circuit(capacitor C3). Capacitor C3 stores the generated voltage210-1.

[0111] Amplifier A4 produces a respective output voltage 210-2 thatis conveyed through switch S34 (activated to ON state) to thenon-inverting input of transconductance amplifier A5 and storagecircuit (capacitor C4). Capacitor C4 stores the voltage 210-2.

[0112] These operations in phase Q1 provide auto-zeroing of theamplifier A4 for subsequent use in phase Q2 used to update andgenerate the amplifier compensation setting 112 stored incapacitors C5 and C6. In other words, the storage circuit (such ascapacitors C3 and C4) store a compensation value (such as one ormore voltage values) that are used to correct input referred offsetassociated with the amplifier A4 when the amplifier A4 issubsequently used to generate the amplifier compensation setting112 in following phase Q2.

[0113] FIG. 5 is an example diagram illustrating generation of afirst amplifier compensation setting according to embodimentsherein.

[0114] As previously discussed, in phase Q2, such as between timeT2 and T3 for cycle #1, the controller 140 produces switch controloutput 322 to be a high state to activate the switches S11, S12,S13, and S14 to an ON state. During phase Q2, the controller 140produces switch control output 323 to be a low state to deactivatethe switches S21, S22, S23, and S24 to an OFF state. During phaseQ2, the controller 140 produces switch control output 321 to be alow state to deactivate the switches S31, S32, S33, and S34 to anOFF state.

[0115] Activation of switch S11 to an ON state in phase Q2 causesthe input signal 182-1 to be inputted to the non-inverting node ofamplifier A4. Activation of switch S12 to an ON state in phase Q2causes the input signal 182-2 to be inputted to the inverting nodeof amplifier A4. Thus, in phase Q2, via activation of the switchesS11 and S12, the controller 140 is operable to: electrically couplethe compensation-setting generator 110 to the input of the secondamplifier 132, and electrically decouple (via deactivation ofswitches S21 and S22) the compensation-setting generator 110 froman input of the first amplifier 131.

[0116] In such an instance, during phase Q2, the amplifier A4produces a respective output voltage 210-1 that is conveyed throughswitch S13 (activated to ON state) to the non-inverting input oftransconductance amplifier A5 and storage circuit (capacitor C5).Capacitor C5 stores the voltage 210-1. The amplifier A4 alsoproduces a respective output voltage 210-2 that is conveyed throughswitch S14 (activated to ON state) to the inverting input oftransconductance amplifier A8 and storage circuit (capacitor C6).Capacitor C6 stores the voltage 210-2.

[0117] The prior stored voltage in capacitors C5 and C6 causes thetransconductance amplifier A8 to provide correction to the voltage210-1 and voltage 210-2 generated by the amplifier A4. Accordingly,the prior stored voltage in capacitors C3 and C4 providescorrection to the amplifier A4 when generating the amplifiercompensation setting 112 stored in capacitors C5 and C6 duringphase Q2.

[0118] FIG. 6 is an example diagram illustrating anautomatic-zeroing (calibration) of the compensation-settinggenerator according to embodiments herein.

[0119] As previously discussed, in phase Q3, such as between timeT3 and T4 for cycle #1, the controller 140 produces switch controloutput 321 to be a high state to activate the switches S31, S32,S33, and S34 to an ON state. During phase Q3, the controller 140produces switch control output 322 to be a low state to deactivatethe switches S11, S12, S13, and S14 to an OFF state. During phaseQ3, the controller 140 produces switch control output 322 to be alow state to deactivate the switches S21, S22, S23, and S24 to anOFF state.

[0120] Activation of switches S31 and S32 to ON states causes thereference voltage Vref to be inputted to both the inverting out andnon-inverting node of amplifier A4. In such an instance, theamplifier A4 produces a respective output voltage 210-1 that isconveyed through switch S33 (activated to ON state as well) to theinverting input of transconductance amplifier A5 and storagecircuit capacitor C3. Capacitor C3 stores the voltage 210-1.

[0121] Amplifier A4 produces a respective output voltage 210-2 thatis conveyed through switch S34 (activated to ON state) to thenon-inverting input of transconductance amplifier A5 and storagecircuit capacitor C4. Capacitor C4 stores the voltage 210-2.

[0122] The operations in phase Q1 provide auto-zeroing of theamplifier A4 for subsequent use in phase Q4 used to update andgenerate the amplifier compensation setting 111 stored incapacitors C1 and C2. In other words, the storage circuit (such ascapacitors C3 and C4) store a compensation value (such as voltagevalues) that are used to correct input referred offset associatedwith the amplifier A4 when the amplifier A4 is subsequently used togenerate the amplifier compensation setting 111 in following phaseQ4.

[0123] FIG. 7 is an example diagram illustrating generation of asecond amplifier compensation setting according to embodimentsherein.

[0124] In phase Q4, such as between time T4 and T5 for cycle #1,the controller 140 produces switch control output 323 to be a highstate to activate the switches S21, S22, S23, and S24 to an ONstate. During phase Q4, the controller 140 produces switch controloutput 322 to be a low state to deactivate the switches S21, S22,S23, and S24 to an OFF state. During phase Q4, the controller 140produces switch control output 321 to be a low state to deactivatethe switches S31, S32, S33, and S34 to an OFF state.

[0125] Activation of switch S21 to an ON state in phase Q4 causesthe input signal 181-1 to be inputted to the non-inverting node ofamplifier A4. Activation of switch S22 to an ON state in phase Q4causes the input signal 181-2 to be inputted to the inverting nodeof amplifier A4. Thus, in phase Q4, via activation of the switchesS21 and S22, the controller 140 is operable to: electrically couplethe compensation-setting generator 110 to the input of the firstamplifier 131, and electrically decouple (via deactivation ofswitches S11 and S12) the compensation-setting generator 110 froman input of the second amplifier 132.

[0126] In such an instance, during phase Q4, the amplifier A4produces a respective output voltage 210-1 that is conveyed throughswitch S23 (activated to ON state) to the inverting input oftransconductance amplifier A3 and storage circuit (capacitor C2).Capacitor C2 stores the voltage 210-1.

[0127] The amplifier A4 also produces a respective output voltage210-2 that is conveyed through switch S24 (activated to ON state)to the non-inverting input of transconductance amplifier A3 andcapacitor C1. Capacitor C1 stores the voltage 210-2.

[0128] The prior stored voltage in capacitors C3 and C4 causes thetransconductance amplifier A5 to provide correction to the voltage210-1 and voltage 210-2 generated by the amplifier A4. Accordingly,the prior stored voltage in capacitors C3 and C4 providescorrection to the amplifier A4 when generating the amplifiercompensation setting 111 stored in capacitors C1 and C2 duringphase Q4.

[0129] FIG. 8 is an example diagram illustrating a more specificimplementation of an amplifier and compensator according toembodiments herein.

[0130] As shown in this example embodiment, and as previouslydiscussed, transconductance amplifier A3 provides correction toamplifier 131 including amplifier A1 and A2. Amplifier 132 can beconfigured to include similar circuitry.

[0131] FIG. 9 is an example diagram illustrating a more specificimplementation of a compensation-setting generator according toembodiments herein.

[0132] As shown in this example embodiment, and as previouslydiscussed, transconductance amplifier A5 provides correction toamplifier A4 in the compensation setting generator 110.

[0133] FIG. 10 is an example block diagram of a computer device forimplementing any of the operations as discussed herein according toembodiments herein.

[0134] As shown, computer system 1000 (such as implemented by anyof one or more resources such as controller 140, compensationsetting generator 110, compensator 121, etc.) of the presentexample includes an interconnect 1011 that couples computerreadable storage media 1012 such as a non-transitory type of media(or hardware storage media) in which digital information can bestored and retrieved, a processor 1013 (e.g., computer processorhardware such as one or more processor devices), I/O interface1014, and a communications interface 1017.

[0135] I/O interface 1014 provides connectivity to any suitablecircuitry such as each of phases 110.

[0136] Computer readable storage medium 1012 can be any hardwarestorage resource or device such as memory, optical storage, harddrive, floppy disk, etc. In one embodiment, the computer readablestorage medium 1012 stores instructions and/or data used by thecontrol application 140-1 to perform any of the operations asdescribed herein.

[0137] Further in this example embodiment, communications interface1018 enables the computer system 1000 and processor 1013 tocommunicate over a resource such as network 193 to retrieveinformation from remote sources and communicate with othercomputers.

[0138] As shown, computer readable storage media 1012 is encodedwith control application 140-1 (e.g., software, firmware, etc.)executed by processor 1013. Control application 140-1 can beconfigured to include instructions to implement any of theoperations as discussed herein.

[0139] During operation of one embodiment, processor 1013 accessescomputer readable storage media 1012 via the use of interconnect1011 in order to launch, run, execute, interpret or otherwiseperform the instructions in control application 140-1 stored oncomputer readable storage medium 1012.

[0140] Execution of the control application 140-1 producesprocessing functionality such as control process 140-2 in processor1013. In other words, the control process 140-2 associated withprocessor 1013 represents one or more aspects of executing controlapplication 140-1 within or upon the processor 1013 in the computersystem 1000.

[0141] In accordance with different embodiments, note that computersystem 1000 can be a micro-controller device, logic, hardwareprocessor, hybrid analog/dif circuitry, etc., configured to controla power supply and perform any of the operations as describedherein.

[0142] Functionality supported by the different resources will nowbe discussed via flowchart in FIG. 10. Note that the steps in theflowcharts below can be executed in any suitable order.

[0143] FIG. 11 is an example diagram illustrating a methodaccording to embodiments herein.

[0144] In processing operation 1110, the controller 140 controlscompensation-setting generator 110 to generate a first amplifiercompensation setting 111 and a second amplifier compensationsetting 112 (during different time slots). In one embodiment, thefirst amplifier compensation setting 111 is generated to correct aninput offset voltage associated with first amplifier 131; thesecond amplifier compensation setting 112 is generated to correctan input offset voltage associated with second amplifier 132.

[0145] In processing operation 1120, the controller 140 applies thefirst amplifier compensation setting 111 to the first amplifier131.

[0146] In processing operation 1130, the controller 140 applies thesecond amplifier compensation setting 112 to the second amplifier132.

[0147] In processing operation 1140, the controller 140 switchesbetween updating the first compensation setting 111 applied to thefirst compensator 121 and the second compensation setting 112applied to the second amplifier 132.

[0148] Note again that techniques herein are well suited for use incircuit applications such as those that include multipleamplifiers. However, it should be noted that embodiments herein arenot limited to use in such applications and that the techniquesdiscussed herein are well suited for other applications aswell.

[0149] Based on the description set forth herein, numerous specificdetails have been set forth to provide a thorough understanding ofclaimed subject matter. However, it will be understood by thoseskilled in the art that claimed subject matter may be practicedwithout these specific details. In other instances, methods,apparatuses, systems, etc., that would be known by one of ordinaryskill have not been described in detail so as not to obscureclaimed subject matter. Some portions of the detailed descriptionhave been presented in terms of algorithms or symbolicrepresentations of operations on data bits or binary digitalsignals stored within a computing system memory, such as a computermemory. These algorithmic descriptions or representations areexamples of techniques used by those of ordinary skill in the dataprocessing arts to convey the substance of their work to othersskilled in the art. An algorithm as described herein, andgenerally, is considered to be a self-consistent sequence ofoperations or similar processing leading to a desired result. Inthis context, operations or processing involve physicalmanipulation of physical quantities. Typically, although notnecessarily, such quantities may take the form of electrical ormagnetic signals capable of being stored, transferred, combined,compared or otherwise manipulated. It has been convenient at times,principally for reasons of common usage, to refer to such signalsas bits, data, values, elements, symbols, characters, terms,numbers, numerals or the like. It should be understood, however,that all of these and similar terms are to be associated withappropriate physical quantities and are merely convenient labels.Unless specifically stated otherwise, as apparent from thefollowing discussion, it is appreciated that throughout thisspecification discussions utilizing terms such as "processing,""computing," "calculating," "determining" or the like refer toactions or processes of a computing platform, such as a computer ora similar electronic computing device, that manipulates ortransforms data represented as physical electronic or magneticquantities within memories, registers, or other information storagedevices, transmission devices, or display devices of the computingplatform.

[0150] While this invention has been particularly shown anddescribed with references to preferred embodiments thereof, it willbe understood by those skilled in the art that various changes inform and details may be made therein without departing from thespirit and scope of the present application as defined by theappended claims. Such variations are intended to be covered by thescope of this present application. As such, the foregoingdescription of embodiments of the present application is notintended to be limiting. Rather, any limitations to the inventionare presented in the following claims.

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